Power Analysis of Novel Glitch Resistant DET-FF

Abstract

In this digital era, the flip flops are widely used for data storage. To increase the flip flops reliability, speed and power consumption, the fault resistant capacity must be improved. Therefore, it is needed to design the flip-flops for lowest average power consumption, smallest delay and area and maximum reliability with fault resistant capacity. Presently, the device scaling reduces the supply voltage requirement, transistor size, device capacitances, node charge and increases clock frequency therefore the circuits become vulnerable to the glitches. Voltage transient as a result of the collected charge is called a transient fault. In memory elements transient faults may be produced by the preceding combinational circuit glitches. Voltage supply scaling is a very efficient step to lower the power consumption. In static CMOS circuit designs, power consumption due to the glitches cannot be ignored as the portion of power consumption varies from 9% to 38% [1]. In the field of digital integrated circuits and systems, the energy-efficient circuit design is one of the great challenge for the researchers [2]. In [3-7] the authors presented novel designs which are reduced great power consumption and provide the fault free output with higher performance results. Clock network consumes more power, therefore, this is necessary to reduce the clock count. To reduce the clock count, the true single phase clock (TSPC) technique has been advised with the basic registers [8]. In [9], the authors proposed DET-FF to overcome the built-in clock overlap threat, by using true single phase clock circuits instead of an inverted clock. Power consumption in clock distribution network is very significant, which may account 45% of the total system power [10]. To reduce the clock power consumption, the clock frequency can be scaled down, by sampling the data on both of the falling and rising edges of the clock, without altering the system throughput. The DET procedure reduce the 50% power dissipation of the clock network system. Although DET designs are more complex as compared to single edge triggered (SET) designs, this can be more energy efficient [11]. The dual data rate flip flop (DDR-FF) has a lower clock load by cause of its simple configuration and lower activity factor because of its hard edge quality factor [12]. DET flip flops provide the equal data rate as SET flip-flops at the half of the clock frequency, which leading reduction in power dissipation of digital synchronous logic designs [13-14]. Therefore, we have presented a novel low power glitch resistant DET-FF which can work accurately at low voltage supply. The rest part of this paper is organized as follows. Section II includes, background study. We have discussed the proposed design in section III. Section IV explains the comparative analysis of different DET-FF designs and finally section V, concludes this work